The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the invention relates to a quantum effect device and a method of manufacturing the quantum effect device, and a semiconductor device obtained by simplifying a binary decision diagram circuit including a single-electron tunneling transistor using semiconductor fine-lines, and a method of manufacturing the semiconductor device.
In these days, there is an increasing demand for decrease of power consumption of LSIs used in personal portable equipment. This is because the decrease of the power consumption of LSIs leads to decrease of power consumption of the entire portable equipment, resulting in elongating an operable time of the equipment driven by batteries. Therefore, the power consumption of a semiconductor device has definitely been decreased.
In a CMOS semiconductor device, which is recently mainly used as a semiconductor device, power consumption P is represented as P=f.multidot.C.multidot.V.sup.2, wherein f indicates an operational frequency of a circuit, C indicates an equivalent capacitance of the entire circuit, and V indicates an operational supply voltage. Therefore, when the operational frequency f is constant, the equivalent capacitance C of the entire circuit and the operational supply voltage V are required to be decreased for the purpose of decreasing the power consumption P. The decrease of the capacitance and the operational voltage corresponds to decrease of the number of carriers to be moved.
Accordingly, in order to decrease the power consumption of a semiconductor device, it is necessary to decrease the number of carriers for transferring a signal. A single-electron tunneling device, which transfers a signal with a single electron, is regarded as an ultimate form for this purpose (Nakazato et: al., IEDM Tech. Digest, p. 487 (1992)). Such a single-electron tunneling device attracts attentions as the most promising device of a post-Si-VLSI. In accordance with the recent development of a fine-line processing technique, it has become possible to form a fine-line structure to the same extent as a wavelength of an electron. Various attempts have been made to express bit information with a device using several electrons and to construct a single-electron tunneling device by extending the present concept of a semiconductor device.
Now, a conventional four-terminal single-electron tunneling device will be described with reference to the accompanying drawings.
FIG. 9(a) is a schematic circuit diagram of a four-terminal single-electron tunneling device to be used in a conventional pseudo CMOS single-electron tunneling circuit (Tucker JR; J. Appl. Phys. 72, 4399 (1992)). As is shown in FIG. 9(a), the conventional four-terminal single-electron tunneling device includes a first tunnel junction 103 connected with a common node 101 at its one electrode and connected with a drain terminal 102 at its another electrode, a second tunnel junction 105 connected with the common node 101 at its one electrode and connected with a source terminal 104 at its another electrode, a first capacitor 107 connected with the common node 101 at its one electrode and connected with a gate terminal 106 at its another electrode, and a second capacitor 109 connected with the common node 101 at its one electrode and connected with a power terminal 108 at its another electrode.
The four-terminal single-electron tunneling device works, for example, as an n-type device when the power terminal 108 is set at a supply voltage VDD and the gate terminal 106 is used as a gate electrode, and as a p-type device when the power terminal 108 is grounded and the gate terminal 106 is used as a gate electrode. Accordingly, a combination of such n-type and p-type four-terminal single-electron tunneling devices can constitute a circuit equivalent to a CMOS circuit. FIG. 9(b) shows simulation results of the operation of the conventional four-terminal single-electron tunneling device, and reveals that a characteristic similar to the Vd-Id characteristic of a MOSFET can be obtained by this single-electron tunneling device.
However, although the conventional single-electron tunneling device transfers a signal with one electron and is regarded as one of the ultimate devices from a view point of the power consumption decrease, it has the following two problems:
The first problem arises in a processing technique. In the case where the device as shown in FIG. 9(a) is realized by using silicon, which is superior in mass-production and material stability, it is necessary to suppress the capacitance of the tunnel junction to be several aF (atto-farad; 1 aF=10.sup.-18 F) as is shown in FIG. 9(b), and hence, a fine-line processing technique on a nm-level is indispensable. In the conventional manufacturing method for a quantum effect device using the electron beam lithography, a line width of approximately 10 nm is the minimum limit. Thus, it is disadvantageously difficult to form a device of several nm or smaller, which can exhibit a remarkable quantum effect. Also, when an electron beam is used, a process damage can be caused on the surface of a silicon substrate, which can disadvantageously degrade the characteristic of the device.
The second problem arises in a circuit technique. The single-electron tunneling device has a different operational mechanism from that of the CMOS technique, which is mainly used for conventional VLSIs, and theoretically has extremely small input and output voltages. Therefore, it is necessary to adopt, in the single-electron tunneling device, a different logical circuit technique from the conventional circuit technique. From this point of view, there is a proposal of forming a binary decision diagram circuit by using a single-electron tunneling transistor (Yoshihito Amamiya, et al., Oyo Butsuri, 64, No. 8, 765-768(1995)).